Test response compaction by an accumulator behaving as a multiple input non-linear feedback shift register
نویسندگان
چکیده
In this paper we show that an accumulator can be modified to behave as a Non-Linear Feedback Shft Register suitable for test response compaction. The hardware required for this modification is less than that required to mod& a register to a Multiple Input Linear Feedback Shgt Register, MISR. We show with experiments on ISCAS’85, ISCAS’89 benchmark circuits and various types of multipliers that the post-compaction fault coverage obtained by the proposed scheme is higher than that of the already known accumulator based compaction schemes and in most cases identical to that achieved using a MISR.
منابع مشابه
Bit-Serial Test Pattern Generation by an Accumulator Behaving as a Non-Linear Feedback Shift Register
Arithmetic function modules which are available in many circuits can be utilized to generate test patterns and compact test responses. Recently, it was shown that an adder or an accumulator cannot be used as a bit serial test pattern generator due to the poor random properties of the generated sequences. Thus, accumulator-multiplier or adder-multiplier structures have been proposed. In this pap...
متن کاملDesign of accumulator Based 3-Weight Pattern Generation using LP-LSFR
The objective of the BIST is to reduce power dissipation without affecting the fault coverage. Weighted pseudorandom built-in self test (BIST) schemes have been utilized in order to drive down the number of vectors to achieve complete fault coverage in BIST applications. Weighted sets comprising three weights, namely 0, 1, and 0.5 have been successfully utilized so far for test pattern generati...
متن کاملBit Swapping Linear Feedback Shift Register For Low Power Application Using 130nm Complementary Metal Oxide Semiconductor Technology (TECHNICAL NOTE)
Bit swapping linear feedback shift register (BS-LFSR) is employed in a conventional linear feedback shirt register (LFSR) to reduce its power dissipation and enhance its performance. In this paper, an enhanced BS-LFSR for low power application is proposed. To achieve low power dissipation, the proposed BS-LFSR introduced the stacking technique to reduce leakage current. In addition, three diffe...
متن کاملAn Efficient Deterministic Test Pattern Compaction Scheme Using Modified IC Scan Chain
In this paper, we propose a new scheme for Built-In Self-Test (BIST) that uses an LFSR obtained by adding feedback loops to the IC boundary scan chain. This LFSR first generates random patterns to cover easy-to-test faults and after the random testing phase it is partially loaded with seeds to generate deterministic vectors for hard-to-test faults. The seeds are obtained by solving systems of l...
متن کاملNon-intrusive BIST for systems-on-a-chip
The term “functional BIST” describes a test method to control functional modules so that they generate a deterministic test set, which targets structural faults within other parts of the system. It is a promising solution for self-testing complex digital systems at reduced costs in terms of area overhead and performance degradation. While previous work mainly investigated the use of functional ...
متن کامل